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Coding & systems
Low Latency
Cache-friendly C++, hot paths, nanoseconds
Overview
About low latency questions in quant interviews
C++ patterns asked at HFT desks: cache-friendly layouts, branch-prediction-aware code, and the hot-path optimisations that separate quant-dev offers from rejections.
How to study this topic
A path that works
- 1
Start with the easy set
Warm up with the 8 easy low latency questions. Quick wins build pattern recognition before complexity ramps.
- 2
Drill the medium tier next
15 medium questions sit in the sweet spot where most interview questions cluster. Time yourself, then redo any you missed two days later.
- 3
Stress-test on hard problems
11 hard questions simulate the on-site round. Skip looking at solutions for at least 20 minutes, then write up your approach.
The library
All 34 low latency questions
easyCompiler Barrier FenceeasyTimespec Elapsed Nanoseconds (clock_gettime Arithmetic Pattern)easyForce-Inline and No-Inline Tick Rounding (__attribute__ Annotation)easyRDTSC Cycle CountereasyZero Copy Binary Parsing with SpaneasyBranch-Free Min/MaxeasyCircular Buffer LoggingeasySoftware Prefetch for Sequential Price Array ScanmediumSIMD Batch FX Price ConversionmediumFlat Array Symbol Table: O(1) Metadata LookupmediumHot/Cold Data Splitting for Cache-Efficient Trade StructmediumLow-Latency Timer Heapmedium4x Loop-Unrolled Exponential Moving AveragemediumFixed-Point Price Arithmetic (FixedPoint<4> with Integer Backend)mediumCache-Oblivious Recursive Matrix Transpose for Correlation MatricesmediumComputed Goto Message Dispatch (GCC Label Address Extension)medium__restrict__ Pointer Alias Hint for Vectorized Price UpdatemediumMarket Data LRU CachemediumHorizontal Sum of Portfolio Positions (Scalar Equivalent of SIMD hadd)mediumRisk Group NettingmediumBranchless Absolute Value via Arithmetic ShiftmediumCRC32 Packet Checksum (Scalar Equivalent of SSE4.2 _mm_crc32_u8)mediumPage Warmup via Sequential Touch (Huge Page Pre-fault Pattern)hardBranchless Order Router: 4-Venue TournamenthardSimplified TCP State Machine (Kernel-Bypass Connection Lifecycle)hardLock-Free Append-Only Timestamp Log (Atomic Fetch-Add Slot Allocation)hardLock-Free SPSC Ring BufferhardTemplate-Inlined Strategy Dispatch (Zero Virtual Overhead)hardSIMD-Accelerated Order Price FilterhardDynamic SIMD-Optimized BitsethardSpeculative Execution Fence for Sequence-Number Guard (lfence / Spectre Mitigation)hardCache-Friendly B+ TreehardO(1) Order Cancel with Doubly-Linked List and Hash MaphardJSON Delimiter Scanner (Scalar Equivalent of simdjson SIMD Byte Search)
View all 34 low latency questionsRelated topics