False Sharing Benchmark - Quant Developer Interview Question
Difficulty: Medium
Category: concurrency
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Topics: concurrency, performance, memory-layout, atomic
Problem Description
False sharing degrades performance in low-latency trading systems when multiple threads modify independent variables residing on the same CPU cache line, triggering excessive cache coherence traffic. Mitigating this requires explicit memory alignment or padding to ensure frequently updated variables are separated by the architecture's cache line size, typically 64 bytes.
Task
Implement the thread-safe class AlignedCounters to manage two independent int64_t atomic counters, ensuring they are sep
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