FPGA Memory Mapped Order Gateway - Quant Developer Interview Question

Problem Description

High-frequency trading systems often interface directly with FPGA hardware via Memory Mapped I/O (MMIO) to minimize latency by bypassing the operating system kernel. This low-level communication requires precise register manipulation and strict memory ordering to ensure trade instructions are executed correctly and efficiently. Task Implement the sendOrder method in the FpgaOrderGateway class to interface with a simulated FPGA device via a memory-mapped pointer. The device is mapped to a provid