Cache-Aligned Atomic Counters - Quant Developer Interview Question

Problem Description

False sharing significantly degrades performance in low-latency trading systems by triggering excessive cache coherence traffic when threads modify independent variables on the same cache line. Mitigating this requires explicit memory alignment to ensure frequently updated atomic counters reside in separate cache lines. Task Implement a struct named CacheAlignedCounters containing two public std::atomic<int> members, a and b, both initialized to 0. Apply alignas using std::hardware_destructive_